1. Field
Exemplary embodiments of the present invention relate to a memory and a method for operating the same.
2. Description of the Related Art
In general, a memory is roughly divided into a volatile memory which may loss input information when power supply is cut off and a nonvolatile memory which may continuously maintain a storage state of input information even though power supply is cut off. The volatile memory may include DRAM and SRAM, and the nonvolatile memory may include a flash memory such as EEPROM. Hereinafter, the nonvolatile memory and the features thereof will be described.
The nonvolatile memory (or particularly a flash memory) programs a memory cell by storing electrons in a conductive band of a floating gate using F-N (Fouler-Nordheim) tunneling in the conductive band. Here, the threshold voltage of the memory cell is increased by electric charge stored in the conductive band of the floating gate. Depending on the value of data to be stored in the memory cell, the level and number of program pulses applied to the floating gate may differ. Therefore, depending on the value of data stored in the memory cell, the amount of electric charge stored in the conductive band of the floating gate differs. That is, the voltage distribution of the threshold voltage of the memory cell differs depending on the value of the data stored therein. For reference, since the characteristics of memory cells inside a nonvolatile memory device are different from each other, even memory cells applied with the same level and number of program pulses have a certain range of threshold voltage distribution, instead of the same threshold voltage.
The nonvolatile memory includes a memory cell array. The memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. Each of the pages includes a plurality of memory cells. The nonvolatile memory performs an erase operation on the basis of memory blocks and performs a write or read operation on the basis of pages.
In the nonvolatile memory, the threshold voltage of a memory cell differs depending on the value of data stored in the memory cell as described above. Therefore, such a characteristic may be used to read the value of the data stored in the memory cell. For example, a single level cell (hereinafter, referred to as SLC) capable of storing one-bit data has an erase state in which erase data is stored or a program state in which program data is stored. The threshold voltage distribution of memory cells in the erase state has a lower average than the threshold voltage distribution of memory cells in the program state. Therefore, a voltage having a level between both voltage distributions may be used to determine whether the data stored in a memory cell is erase data or program data.
Here, the threshold voltage distribution of memory cells in which data having the same value are stored is to be constant at all times, in order to output the data stored in the memory cells with precision. However, with the increase in integration degree of memory cells, the distance between the memory cells has been reduced to such a level that the threshold voltage of a memory cell is influenced by the value of data stored in an adjacent memory cell. Such a phenomenon is referred to as cell interference. The reason why the cell interference occurs is that the threshold voltage of a memory cell may be influenced by a program pulse applied to an adjacent memory cell, because of parasitic capacitance existing between the memory cells.
FIG. 1 is a diagram showing change in threshold voltage distributions, caused by cell interference. In a first distribution, a solid line 101 indicates the threshold voltage distribution of memory cells which are not influenced by cell interference, among memory cells storing erase data, and a dotted line 102 indicates the threshold voltage distribution of memory cells which are influenced by the cell interference, among the memory cells storing erase data. In a second distribution, a solid line 103 indicates the threshold voltage distribution of memory cells which are not influenced by cell interference, among memory cells storing program data, and a dotted line 104 indicates the threshold voltage distribution of memory cells which are influenced by the cell interference, among the memory cells storing program data.
Referring to FIG. 1, when program data is stored in a memory cell, a threshold voltage of an adjacent cell may be influenced and increased by program pulses applied to the memory cell. Therefore, the threshold voltage distribution of influenced memory cells becomes higher than the original distribution (102, 104). Here, the threshold voltage distribution increases in accordance with the increase in the level and number of the program pulses.
The cell interference may cause an error of a read operation. Therefore, research has been conducted on technology relating to various interference compensation read operations in order to reduce an error of a read operation, caused by cell interference.